Semiconductor technologies continue to evolve. Computing and communications designs are incorporating more functionality, higher processing and transmission speeds, smaller sizes, more memory, etc., into smaller and more robust architectures. These trends have placed particular demands on interconnect architectures.
Semiconductor memories in particular are evolving at a rapid pace. Memory devices have reduced power requirements, increased capacities, increased operating frequencies, reduced latencies, etc., all while ramping with the exponential density increases according to Moore's Law. To compensate for the increased capabilities of memories, high-speed serial links can be used to couple memories with memory controllers.
High-speed serial links conventionally require training prior to use. High-speed serial links combine data signals, clock timing, control information, etc. through the same “in-band” link. This may pose a problem as conventional memory devices (e.g., DRAM or host controller) have internal registers that need to be set up prior to link training. Registers may be set for diagnostic purposes or to set operation modes.
Traditionally the internal registers are set by using a separate “out-of-band” interface, typically a serial interface with two to five wires. In pin count constrained applications such as DRAMs this can be a significant problem.
In a conventional DRAM system there are two independent input paths and protocol engines, one each for the in-band and out-of-band interfaces. While memory array data is transmitted through the in-band input path and protocol engine, read data from internal registers is returned to the out-of-band protocol engine and driven back a host controller. This requires a separate IO (input/output) port dedicated to register access. What is needed is a way to access DRAM without requiring link training or a separate IO port.